The present invention relates to heterojunction bipolar transistors including those connected in parallel and methods for fabricating the same. The invention also relates to a high-frequency transmitter or receiver having a heterojunction bipolar transistor as an amplifier.
As a high-power device for microwave band, there has been developed GaAs-based heterojunction bipolar transistors (hereinafter, referred to as HBTs). Generally, HBTs, which are high in thermal resistance, have a problem that when used as a high-power device, HBTs would involve high junction temperature. On this account, as shown in FIG. 22, a structure for improving heat radiation property has been proposed in Japanese Patent Laid-Open Publication HEI 8-279562. FIG. 22A shows a planar pattern of HBTs connected in parallel for high-power operation, and FIG. 22B shows a cross section taken along a line Bxe2x80x94B of FIG. 22A. In this structure, a plurality of HBTs 90 each having a collector electrode 106, a base electrode 105 and an emitter electrode 104 are included on the surface side of a GaAs substrate 113, where via holes 110 are provided between adjacent HBTs 90 so as to be cut through the substrate from its top to rear surface side. Heat generated at a junction 127 on the top surface side of each HBT 90 is conducted from the emitter electrode 104 of the transistor to a metal body 99 within its adjacent via holes 110 via an air bridge 111, and further conducted from the metal body 99 to a plated heat sink (hereinafter, referred to as PHS) layer 112 provided on the substrate rear surface, thus being radiated.
However, this conventional structure has a first drawback that for implementation of even higher power output, electric resistance of the air bridge 111 is not negligible, with heat radiation effect insufficient, so that the junction temperature inside the transistor cannot be reduced sufficiently. In this conventional structure, there is a second drawback that because of limitations in reducing the emitter inductance, there may arise variations in high frequency characteristics or the gain in high frequency operation may decline.
Accordingly, an object of the present invention is to provide a heterojunction bipolar transistor (including those connected in parallel) which is capable of improving the heat radiation and reducing the emitter inductance.
Another object of the invention is to provide a fabricating method capable of fabricating such a heterojunction bipolar transistor.
A further object of the invention is to provide a high-frequency transmitter or receiver having such a heterojunction bipolar transistor as an amplifier.
In order to achieve the above-mentioned object, the present invention provides a heterojunction bipolar transistor comprising: an emitter layer, a base layer and a collector layer laminated on a top surface of a semiconductor substrate; and a heat sink layer made of a metal and provided on a rear surface of the substrate, wherein a via hole is cut through the emitter layer, the base layer, the collector layer and the substrate, and a surface electrode of the emitter layer and the heat sink layer are connected to each other by a metal wiring line running through within the via hole.
In the heterojunction bipolar transistor of this invention, heat generated during operation at junctions (mainly, an interface between the base layer and the collector layer) on the top surface side of the semiconductor substrate is dissipated through two paths. One of the paths is a path along which the heat conducts from the junction via the surface electrode of the emitter layer to the metal wiring line on the substrate top surface side, and further conducts from the metal wiring line within the via hole to the heat sink layer on the substrate rear surface side. The other path is a path along which heat conducts from the junction via an interior of the substrate to the metal wiring line within the via hole, and further conducts from there to the heat sink layer on the substrate rear surface side. Since the heat generated at the junction is dissipated through two paths as described above, heat radiation property of the heterojunction bipolar transistor is improved. Also, since the via hole extends through the emitter layer, the base layer, the collector layer and the substrate, the surface electrode of the emitter and the top surface of the via hole are very close to each other. Therefore, the metal wiring line is led from the surface electrode of the emitter layer into the via hole at a very short distance. As a result, emitter inductance is reduced and high-frequency characteristics are improved, as compared with the case where an air bridge is used.
In an embodiment of the invention, the via hole has a cross section formed into a polygonal shape in which apex angles are obtuse angles, or a circular shape.
When the cross-sectional shape of the via hole has acute angles, there is a possibility that electric field concentration may occur at the acute-angle portions during operation, causing the device reliability to lower. Thus, in the heterojunction bipolar transistor of this embodiment, the via hole has a cross section formed into a polygonal shape in which apex angles are obtuse angles, or a circular shape. As a result, electric field concentration around the via hole is suppressed. Therefore, the device reliability is improved.
In an embodiment of the invention, an interior of the via hole is buried with a same material as that of the metal wiring line.
In the heterojunction bipolar transistor of this embodiment, since the interior of the via hole is buried with the same material as that of the metal wiring line, the heat radiation effect through the via hole is enhanced, so that the heat radiation property is further improved. As a result, stabler device characteristics as well as higher device reliability can be obtained.
In an embodiment of the invention, a peripheral edge portion of the emitter layer is formed so as to be thinner in thickness than residual portion of the emitter layer.
In the heterojunction bipolar transistor of this embodiment, the thickness of the peripheral edge portion of the emitter layer is thinner than the thickness of the residual portion of the emitter layer, that is, what we called an edge-thinning structure is formed. Therefore, re-combination of holes and electrons generated between the peripheral edge portions of the emitter layer and the base layer during operation is prevented. As a result, the device reliability can be enhanced.
In an embodiment of the invention, a plurality of heterojunction bipolar transistors are arrayed on a common semiconductor substrate and electrically connected to one another so as to be enabled to operate in parallel.
In this parallel-connected heterojunction bipolar transistors, since any of the heterojunction bipolar transistors are electrically connected to one another so as to be enabled to operate in parallel, a high-power output operation is enabled. Also, heat generated at the junction of each transistor is dissipated to the heat sink layer on the substrate rear surface. Therefore, heat concentration due to performance variations among the transistors is suppressed so that the reliability is improved.
In an embodiment of the invention, a groove extending from the top surface of the substrate to the rear surface of the substrate is provided in the common semiconductor substrate so as to partition adjacent heterojunction bipolar transistors from one another.
Generally, in parallel-connected heterojunction bipolar transistors, adjacent transistors would thermally affect one another during operation. When one transistor is unequally heated with the result of nonuniform heat generation, a transistor adjacent to the transistor is affected with the result of heat generation, which in some extreme cases leads to breakage. Also, when no transistor is present in adjacency to one transistor, there is a possibility that the thermal balance collapses, leading to a similar result. Therefore, in the parallel-connected heterojunction bipolar transistors of this embodiment, a groove which extends from top surface to rear surface of the substrate is provided in the common semiconductor substrate so as to partition adjacent heterojunction bipolar transistors from each other. As a result, adjacent heterojunction bipolar transistors are thermally shielded from each other during operation, thus never affecting each other thermally. Moreover, the transistors are uniformized in heat capacity, thus operating uniformly. Therefore, the device reliability can be improved.
The present invention also provides a method for fabricating a heterojunction bipolar transistor, comprising the steps of: laminating a collector layer, a base layer and an emitter layer in this order on a top surface side of a semiconductor substrate; patterning the collector layer, the base layer and the emitter layer so that an area of an upper layer among the collector layer, the base layer and the emitter layer may become smaller; forming a surface electrode for ohmic contact on each surface portion of the collector layer, the base layer and the emitter layer; forming a first via hole which extends through the emitter layer, the base layer and the collector layer and ends at a specified depth within the substrate; forming a metal wiring line which extends from the surface electrode of the emitter layer to within the first via hole so as to reach a bottom portion of the first via hole; polishing a rear surface side of the substrate up to the bottom portion of the first via hole; and providing a heat sink layer made of a metal on the polished rear surface of the substrate so that the heat sink layer makes contact with the metal wiring line within the first via hole.
According to the heterojunction bipolar transistor fabricating method of this invention, the heterojunction bipolar transistor capable of reducing the heat radiation property and reducing the emitter inductance is fabricated.
In an embodiment of the invention, after forming the first via hole, an insulating film is so provided as to cover top surfaces and side surfaces of the emitter layer, the base layer and the collector layer, and the first via hole is furthermore extended toward the rear surface side of the substrate.
In the process of forming the first via hole, a long-time etching process is performed in order for the first via hole to cut through the emitter layer, the base layer and the collector layer and to reach up to a specified depth within the substrate. Therefore, there occurs a dimensional shift due to lateral expansion of the etching, which causes the device processing accuracy to lower and characteristic variations to occur. Also, there appears a rough surface in the inner wall of the first via hole i.e. rough side surfaces of the emitter layer, the base layer and the collector layer. Particularly with the use of dry etching, plasma damage would be led to the etching surfaces. Therefore, there is a possibility of deterioration in device characteristics.
Thus, in the heterojunction bipolar transistor fabricating method of this embodiment, after forming the first via hole which extends through the emitter layer, the base layer and the collector layer, an insulating film is so provided as to cover top surfaces and side surfaces of the emitter layer, the base layer and the collector layer. The first via hole is furthermore extended toward the rear surface side of the substrate. As a result, dimensional shifts of the first via hole due to the etching are suppressed, so that higher device accuracy and higher characteristic uniformization can be obtained. Further, occurrence of surface roughnesses and damage on the side surfaces of the emitter layer, the base layer and the collector layer can be eliminated. Therefore, higher device reliability can be obtained.
In an embodiment of the invention, a wet etching process or a low-power conditioned dry etching process is performed in the step of forming the first via hole, and a high-power conditioned dry etching is performed in the step of extending the first via hole toward the rear surface side of the substrate.
In the heterojunction bipolar transistor fabricating method of this embodiment, a wet etching process or a low-power conditioned dry etching process is performed in the step of forming the first via hole, so that occurrence of rough surface and damage at the side surfaces of the emitter layer, the base layer and the collector layer can be effectively prevented. Therefore, higher device reliability can be obtained. Also, a high-power conditioned dry etching is performed in the step of extending the first via hole toward the rear surface side of the substrate, so that a high-speed etching process can be achieved and the lateral expansion due to etching is suppressed. Thus, the first via hole can be deeply formed in a relatively short time.
In an embodiment of the invention, an undercut is formed by etching a lower outer-edge portion of the emitter layer in the process of patterning the emitter layer; a metal film is deposited on the top surface side of the substrate so as to form the surface electrode of the base layer, with an inner edge of the surface electrode of the base layer formed in self alignment to the emitter layer by using the undercut; and the metal film and the base layer are continuously etched with the same mask so that an outer edge of the surface electrode of the base layer and an outer edge of the base layer become coincident with each other.
In the heterojunction bipolar transistor fabricating method of this invention, since the first via hole extends through the emitter layer, the base layer and the collector layer, the individual layers and their surface electrodes surround the periphery of the first via hole in an elongate and annular form. Therefore, there is a possibility that the base wiring resistance especially increases, which causes the high-frequency characteristics of the device to deteriorate. Although the increase in base wiring resistance can be suppressed merely by broadening the width of the base layer in order to broadening the area of the surface electrode of the base layer, the base-collector capacity increases and consequently the high-frequency characteristics is lowered.
according to the heterojunction bipolar transistor fabricating method of this embodiment, an undercut is formed by etching a lower outer-edge portion of the emitter layer in the process of patterning the emitter layer, and a metal film is deposited on the top surface side of the substrate so as to form the surface electrode of the base layer, with an inner edge of the surface electrode of the base layer formed in self alignment to the emitter layer by using the undercut. In addition to this, in this embodiment, the metal film and the base layer are continuously etched with the same mask so that an outer edge of the surface electrode of the base layer and an outer edge of the base layer become coincident with each other. As a result, the width of the surface electrode of the base layer can be broadened fully to a range from the outer edge of the emitter layer to the outer edge of the base layer without broadening the width of the base layer. Consequently, increases in the base wiring resistance can be suppressed while increases in the base-collector capacity are avoided. Therefore, high-frequency characteristics of the device can be improved.
In an embodiment of the invention, the first via hole is formed after forming the surface electrodes of the collector layer and the base layer and before forming the surface electrode of the emitter layer; simultaneously with time when the surface electrode of the emitter layer is formed, a wiring pattern of a same material as that of the surface electrode is formed, the wiring pattern extending from a surface portion of the emitter layer to within the first via hole so as to reach a bottom portion of the first via hole; and the metal wiring line is formed on the wiring pattern by a plating process.
In the heterojunction bipolar transistor fabricating method of this embodiment, when forming the surface electrode of the emitter layer, the wiring pattern for plating the metal wiring line is simultaneously formed. Therefore, the process of the metal wiring line can be reduced, as compared with the case where the surface electrode of the emitter layer and the metal wiring line are patterned independently of each other. Accordingly, fabricating cost can be reduced.
In an embodiment of the invention, after forming the metal wiring line, the rear surface side of the substrate is not polished or the rear surface side of the substrate is polished to a specified extent; a second via hole is so formed as to extend from the rear surface side of the substrate up to the bottom portion of the first via hole; and the heat sink layer made of a metal is provided on the rear surface of the substrate so as to make contact with the metal wiring line within the first via hole through the second via hole.
According to the heterojunction bipolar transistor fabricating method of this embodiment, the polishing process or the rear surface of the substrate can be omitted, or needs only to be done to a small polishing extent.
In an embodiment of the invention, simultaneously with time when the first via hole is formed, an alignment hole deeper than the first via hole is formed from the top surface side of the substrate toward the rear surface side of the substrate in a region other than regions occupied by the emitter layer, the base layer and the collector layer; the rear surface of the substrate is polished up to a bottom portion of the alignment hole; and a photolithography process for forming the second via hole is performed with reference to the alignment hole appearing on the rear surface side of the substrate.
In the heterojunction bipolar transistor fabricating method of this embodiment, the second via hole to be formed from the rear surface side of the substrate can be aligned with the first via hole formed from the top surface side of the substrate with a normal aligner instead of any special device such as a double-sided aligner. Therefore, high-accuracy alignment by normal photolithography techniques can be achieved.
In an embodiment of the invention, the second via hole is formed in a conical shape which broadens toward the heat sink layer on the substrate rear surface, and an interior of the second via hole is buried with a same material as that of the heat sink layer.
Since the second via hole is formed in a conical shape which broadens toward the heat sink layer on the substrate rear surface, and buried with a same material as that of the heat sink layer, the heat radiation path substantially increases up to the heat sink layer, so that the heat radiation property can be further improved.
In an embodiment of the invention,
the surface electrodes of the collector layer, the base layer and the emitter layer are each formed by a lift-off process into a patterned surface electrode which surround a periphery of a region where the first via hole is to be formed and a portion of which is cut out.
In the heterojunction bipolar transistor fabricating method of this embodiment, patterns of the surface electrodes are generally annular with part of each pattern cut out. Therefore, a solution of lift-off resist easily penetrates from outside to inside of the generally annular patterns through the cutout portions. Thus, the lift-off process can be achieved more easily, as compared with the case where the surface electrode patterns of the collector layer, the base layer and the emitter layer are completely annular patterns.
In an embodiment of the invention, in the process of polishing the rear surface of the substrate up to the bottom portion of the first via hole, the polishing process is ended, by observing electric resistance of a polishing liquid, at a time point when cut chips of the metal wiring line within the first via hole mingle into the polishing liquid, causing the electric resistance of the polishing liquid to show a change.
According to the heterojunction bipolar transistor fabricating method of this embodiment, since the end point of polishing process is determined by change in electric resistance of the polishing liquid, the end point of polishing process is clarified. Therefore, the accuracy of polishing extent on the rear surface side of the substrate is improved.
In an embodiment of the invention, a plurality of sets of the emitter layer, the base layer and the collector layer of the heterojunction bipolar transistor are arrayed on a common semiconductor substrate; and before the first via hole is formed in each heterojunction bipolar transistor, a device isolation region having a specified thickness is formed between the collector layers of adjacent heterojunction bipolar transistors by performing ion implantation.
Lamination of the emitter layer, the base layer and the collector layer of each heterojunction bipolar transistor is formed into a mesa shape in this heterojunction bipolar transistor fabricating method. Therefore, when the photolithography process is performed to form the first via hole, the film thickness of the photoresist mask would become nonuniform due to the mesa step gap, with the result that the photoresist mask becomes thin in film thickness on the uppermost emitter layer. As a result, there is a possibility that mask break may occur during the etching of the first via hole, causing the emitter layer to be etched. In addition, since merely thickening the film thickness of the photoresist mask would cause the patterning precision to lower, the photoresist mask cannot be thickened so much.
In the heterojunction bipolar transistor fabricating method of this embodiment, therefore, a device isolation region having a specified thickness is formed between the collector layers of adjacent heterojunction bipolar transistors by performing ion implantation. When the photolithography process for forming the first via hole, step gaps between the transistor portions and the field portions i.e. regions between transistors on the substrate are reduced by virtue of the thickness of the device isolation region so that the photoresist mask is uniformized in film thickness. Therefore, during the process of etching the first via hole, the possibility of occurrence of mask break can be eliminated. Still, the successful coverage property of the transistor portions can be obtained during the formation of the metal wiring line, so that the device reliability can be enhanced.
It is desirable to use anti-activated ions such as oxygen ions, helium ions, hydrogen ions, as ions to be implanted for the formation of the device isolation region, in order that the device isolation region is formed into a high-resistance region.
In an embodiment of the invention, a high-frequency transmitter or receiver includes, as a high-frequency amplifier, the heterojunction bipolar transistor, the parallel connected heterojunction bipolar transistors or the heterojunction bipolar transistor made by the heterojunction bipolar transistor fabricating method as described above.
In the high-frequency transmitter or receiver, since the high-frequency amplifier is superior in heat radiation property, high-power output operation with a high gain is enabled in high-frequency amplifications. Also, an enhanced reliability can be obtained.